When a capacitively loaded CMOS port transitions to ground potential, large amounts of charge are rapidly injected into the local ground plane ("Vss") of the integrated circuit ("IC"). Because charge is injected faster than it can be dissipated, Vss experiences a momentary jump in voltage. This is known as "ground bounce."
Ground bounce may cause errors within the IC and can degrade the certainty of IC logic. For example, internal flip-flops sometimes rely upon Vss as a reference voltage. If Vss bounces while it is used as a voltage reference, signals evaluated with reference to Vss may be mistakenly categorized.
The instantaneous relationship between current ("i"), voltage ("v"), and capacitance ("C") can be expressed as: EQU i=C dv/dt,
while the associated expression relating voltage and inductance ("L") is given by: EQU v=L di/dt.
These expressions show that increasing the discharge time, the "dt" term, will reduce the peak current and the peak voltage and reduce, therefore, the ground bounce.
A variety of methods have been offered to decrease ground bounce. Some techniques reduce the current drive capacity of a single pull-down transistor by decreasing its channel width. Such methods however, often degrade the high-speed performance of the circuit.
Other methods suggest the use of parallel pull-down transistors, but many utilize complicated control circuitry to match charge dissipation rates to the magnitude of the impulse or particular desired waveform shapes. For example, in U.S. Pat. No. 5,218,239 to Boomer, a variety of control inputs are purportedly used to switch transistors to provide a digitally selectable choice of transition times.
Other systems vary the voltage to the gates of the pull-down transistors to slowly turn on multiple charge dissipation routes. Examples of such methods are purportedly taught in U.S. Pat. No. 5,124,579 to Naghshineh.
The prior art has generally focused on the field of high speed circuitry where ground bounce is implicated by parasitic capacitive and inductive characteristics. In the area of game port peripheral switching, however, ground bounce is caused when large capacitive loads are intentionally used to map joystick coordinates. Unlike DRAM design where parasitic capacitances of hundreds of pico-farads must be regulated, joystick loads present many thousands of intentionally stored pico-farads of charge. Consequently, many of the offered ground bounce solutions are not adapted for game port peak current control. What is needed therefore, is an inexpensive and simple circuit to reduce peak transition currents on capacitively loaded game ports.